누군가 피워놓은 모닥불

NVIC(Nested vectored interrupt controller)

• up to 81 interrupts (depends on the STM32 device type, refer to the datasheets)

• A programmable priority level of 0-15 for each interrupt. A higher level corresponds to a

lower priority, so level 0 is the highest interrupt priority

• Level and pulse detection of interrupt signals

• Dynamic reprioritization of interrupts

• Grouping of priority values into group priority and subpriority fields

• Interrupt tail-chaining

• An external Non-maskable interrupt (NMI)

NVIC->IP[28]=0x10; // Interrupt priority registers (NVIC_IPRx)

IPR은 하위 4비트(bit[0.3])는 무시, 상위 4비트로 인터럽트 간의 우선순위를 따진다. 인터럽트가 동시에 왔을 때 이 레지스터를 통해 인터럽트 번호가 빠른 것부터 실행한다.

NVIC->ISER[0]|=(1UL<<28);

Interrupt Pending

 ARM 계열뿐 아니라 대부분 CPU는 새로운 interrupt가 걸리면 해당 interrupt flag를 set하고 interrupt routine으로 진입함과 동시에 해당 interrupt flag를 clear시킵니다. 그런데 소프트웨어적으로 interrupt를 금지 시켰거나 혹은 그 해당 interrupt보다 높은 순위의 interrupt를 처리하고 있는중일 경우 곧장 새로운 interrupt를 처리하려고 interrupt service routine으로 분기한다면 interrupt 금지나 그보다 높은 순위의 interrupt라는 개념이 소용이 없게 되어버립니다. 그래서 이럴 경우에는interrupt flag만 set시켜준 상태에서 interrupt 허가조건이 성립될 때까지 새로운 인터럽트를 보류(pending)시키게 됩니다. 이 상황을 'interrupt pending된 상태' 라고 합니다

TIM2->CR1 &= ~(0x7<<4);

[Bits 6:5] CMS: Center-aligned mode selection

00: Edge-aligned mode. The counter counts up or down depending on the direction bit (DIR).

01: Center-aligned mode 1. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set

only when the counter is counting down.

10: Center-aligned mode 2. The counter counts up and down alternatively. Output compare

interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set

only when the counter is counting up.

11: Center-aligned mode 3. The counter counts up and down alternatively. Output compare

interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set

both when the counter is counting up or down.

Note: It is not allowed to switch from edge-aligned mode to center-aligned mode as long as

the counter is enabled (CEN=1)

Bit 4 DIR: Direction

0: Counter used as upcounter

1: Counter used as downcounter

Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder Mode.

TIM2->ARR = 1000-1;

TIM2->PSC = 72-1;

TIM2->EGR |= 0x1;

[Bit 0] UG: Update generation

This bit can be set by software, it is automatically cleared by hardware.

0: No action

1: Re-initialize the counter and generates an update of the registers. Note that the prescaler

counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared if

the center-aligned mode is selected or if DIR=0 (upcounting), else it takes the auto-reload

value (TIMx_ARR) if DIR=1 (downcounting).

TIM2->CR1|=0x1;

TIM2->DIER|=0x1;

[Bit 0 CEN] Counter enable

0: Counter disabled

1: Counter enabled

Note: External clock, gated mode and encoder mode can work only if the CEN bit has been

previously set by software. However trigger mode can set the CEN bit automatically by

hardware.

CEN is cleared automatically in one-pulse mode, when an update event occurs.

[Bit 0] UIE: Update interrupt enable

0: Update interrupt disabled.

1: Update interrupt enabled.

TIMx status register (TIMx_SR)

[Bit 0] UIF : Update Interrupt Flag

– This bit is set by hardware on an update event. It is cleared by software.

0: No update occurred.

1: Update interrupt pending. This bit is set by hardware when the registers are updated:

– At overflow or underflow and if the UDIS=0 in the TIMx_CR1 register.

– When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and

  UDIS=0 in the TIMx_CR1 register.

– When CNT is reinitialized by a trigger event (refer to the synchro control register description),

  if URS=0 and UDIS=0 in the TIMx_CR1 register.

TIMx DMA/Interrupt enable register (TIMx_DIER)

[Bit 0] UIE: Update interrupt enable

0: Update interrupt disabled.

1: Update interrupt enabled.